(1) Field of the Invention
This invention relates generally to ring oscillator circuits and relates more particularly to a CMOS on-chip chain ring oscillator being insensitive to ground noise and having a constant 50% duty cycle over temperature and process variations.
(2) Description of the Prior Art
Ring oscillators are used for a variety of purposes. Usually ring oscillators are used as an internally generated clocking source, or as a stage in a more complex system such as a voltage controlled oscillator (VCO) or a phase locked loop (PLL).
FIG. 1 prior art shows a block diagram of a 7-stage CMOS inverter chain ring oscillator. Normally the number of stages is an odd number with the output of the cascade fed back to the input of the inverter chain. An oscillator provides an output at a specific frequency with no input signal required. The frequency of the oscillator shown at FIG. 1 prior art is completely dependent on the inherent inverter time delay and is therefore not externally controllable.
Each stage of the ring oscillators shown in FIG. 1 prior art has a unity voltage gain and 360/7 degrees of phase shift.
It is obvious that any noise from any source is spreading through the oscillator and that changes of the temperature impacts the electrical properties of the inverter stages and hence impacts frequency and duty cycles of the ring oscillator.
It is a challenge for the engineers to build ring oscillators being insensitive in regard of noise and changes of temperature.
There are patents known in the area of ring oscillators:
U.S. Pat. No. 6,828,866 to Liu teaches a ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g., a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e.g., a ground terminal). The first and second current sources reduce the coupling of noise from the first power supply terminal to the output. The third current source reduces the coupling of noise from the second power supply terminal to the output.
U.S. Pat. No. 6,683,504 to Abernathy discloses a ring oscillator integrated circuit comprising a plurality of parallely arranged ring oscillator sections, where a ring oscillator section can be any conventional ring oscillator circuit. That is, the inputs and the outputs of a plurality of conventional ring oscillators are connected together. Since each ring oscillator section output signal includes random noise, the parallel arrangement of ring oscillators, and the summing of several oscillator signals, causes at least some noise cancellation. As a result, a lower noise oscillator signal is supplied. A method of reducing random noise in a ring oscillator circuit is also provided.
U.S. Pat. No. 6,650,191 to Branch et al. discloses a low power and low jitter CMOS ring oscillator having a novel architecture that includes fully symmetrical differential current steering delay cells. This novel ring oscillator includes a first capacitor coupled between the first power supply rail and a bias voltage input. At least one stage couples across the first capacitor. Each stage includes a first transistor, a second capacitor, and a fully symmetrical differential delay cell. In an embodiment, the first transistor may be a PMOS transistor, where the drain of the first PMOS transistor connects to the first power supply rail and the gate of the first PMOS transistor couple to the bias voltage input. The second capacitor couples between the source of the first transistor and ground and acts as a low pass filter. As a result, the second capacitor minimizes the effects of the thermal and flicker noise of the devices, which provide the tail current. The fully symmetrical differential delay cell includes a control input, a differential input and a differential output. The control input couples to the source of the first PMOS transistor. When one stage is present, the differential input couples to the differential output. When more than one stage is present, the differential outputs couple to the differential inputs of the concurrent delay cell. In addition, the delay cell in the last stage couples to the differential input of the delay cell in the first stage.